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1. general description the DAC1201D125 is a dual-port, high-speed, 2-channel cmos digital-to-analog converter (dac), optimized for high dynamic performance with low power dissipation. supporting an update rate of up to 125 msps, the DAC1201D125 is suitable for direct if applications. separate write inputs allow data to be written to the two dac ports independently of one another. two separate clocks contro l the update rate of each dac port. the DAC1201D125 can interface two separate data ports or one single interleaved high-speed data port. in interleaved mode, the input data stream is demultiplexed into its original i and q data and latched. the i and q data is then converted by the two dacs and updated at half the input data rate. each dac port has a high-impedance differential current output, suitable for both single-ended and differential a nalog output configurations. the DAC1201D125 is pin compatible with the ad9765, dac2902 and dac5662. 2. features and benefits 3. applications DAC1201D125 dual 12-bit dac , up to 125 msps rev. 03 ? 2 july 2012 product data sheet ? dual 12-bit resolution ? typical 185 mw power dissipation ? 125 msps update rate ? 16 mw power-down ? single 3.3 v supply ? sfdr: 81 dbc; f o = 1 mhz; f s =52msps ? dual-port or interleaved data modes ? sfdr: 78 dbc; fo = 10.4 mhz; fs = 78 msps ? 1.8 v, 3.3 v and 5 v compatible digital inputs ? sfdr: 74 dbc; f o = 1 mhz; f s = 52 msps; ? 12 dbfs ? internal and exte rnal reference ? lqfp48 package ? 2 ma to 20 ma full-scale output current ? industrial temperature range of ? 40 ? cto+85 ? c ? quadrature modulation ? direct digital frequency synthesis ? medical/test instrumentation ? arbitrary waveform generator ? direct if applications
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 4. ordering information 5. block diagram table 1. ordering information type number package name description version DAC1201D125hl lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 fig 1. block diagram 001aai976 v dda db11 to db0 refio da11 to da0 DAC1201D125 dac a latch dac a dac b latch dac b reference control amplifier avires agnd v ddd dgnd bvires gainctrl pwd ioutbp ioutbn ioutap ioutan 12 12 input a latch input b latch 12 12 12 wrta/iqwrt clka/iqclk wrtb/iqsel clkb/iqreset 12
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration sot313-2 (lqfp48) DAC1201D125hl da11 n.c. da10 n.c. da9 db0 da8 db1 da7 db2 da6 db3 da5 db4 da4 db5 da3 db6 da2 db7 da1 db8 da0 db9 n.c. mode n.c. v dda dgnd ioutap v ddd ioutan wrta/iqwrt avires clka/iqclk refio clkb/iqreset gainctrl wrtb/iqsel bvires dgnd ioutbn v ddd ioutbp db11 db10 agnd pwd 001aai975 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 table 2. pin description symbol pin type [1] description da11 1 i dac a, data input bit 11 (msb) da10 2 i dac a, data input bit 10 da9 3 i dac a, data input bit 9 da8 4 i dac a, data input bit 8 da7 5 i dac a, data input bit 7 da6 6 i dac a, data input bit 6 da5 7 i dac a, data input bit 5 da4 8 i dac a, data input bit 4 da3 9 i dac a, data input bit 3 da2 10 i dac a, data input bit 2 da1 11 i dac a, data input bit 1 da0 12 i dac a, data input bit 0 (lsb) n.c. 13 not connected
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps [1] type description: s = supply; g = groun d; i = input; o = output; i/o = input/output. n.c. 14 not connected dgnd 15 g digital ground v ddd 16 s digital supply voltage wrta/iqwrt 17 i input write port a/input write iq in interleaved mode clka/iqclk 18 i input clock port a/i nput clock iq in interleaved mode clkb/iqreset 19 i input clock port b/reset iq in interleaved mode wrtb/iqsel 20 i input write port b/select iq in interleaved mode dgnd 21 g digital ground v ddd 22 s digital supply voltage db11 23 i dac b, data input bit 11 (msb) db10 24 i dac b, data input bit 10 db9 25 i dac b, data input bit 9 db8 26 i dac b, data input bit 8 db7 27 i dac b, data input bit 7 db6 28 i dac b, data input bit 6 db5 29 i dac b, data input bit 5 db4 30 i dac b, data input bit 4 db3 31 i dac b, data input bit 3 db2 32 i dac b, data input bit 2 db1 33 i dac b, data input bit 1 db0 34 i dac b, data input bit 0 (lsb) n.c. 35 not connected n.c. 36 not connected pwd 37 i power-down mode enable input agnd 38 s analog ground ioutbp 39 o dac b current output ioutbn 40 o complementary dac b current output bvires 41 i adjust dac b for full-scale output current gainctrl 42 i gain control mode enable input refio 43 i/o reference voltage input/output avires 44 i adjust dac a for full-scale output current ioutan 45 o complementary dac a current output ioutap 46 o dac a current output v dda 47 s analog supply voltage mode 48 i select between dual-port or interleaved mode table 2. pin description ?continued symbol pin type [1] description
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 7. limiting values [1] all supplies are connected together. 8. thermal characteristics 9. characteristics table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max un it v ddd digital supply voltage [1] ? 0.3 +5.0 v v dda analog supply voltage [1] ? 0.3 +5.0 v ? v dd supply voltage difference between analog and digital supply voltage ? 150 +150 mv v i input voltage digital inputs referenced to dgnd ? 0.3 +5.5 v pins refio, avires, bvires referenced to agnd ? 0.3 +5.5 v v o output voltage pins ioutap, ioutan, ioutbp and ioutbn referenced to agnd ? 0.3 v dda + 0.3 v t stg storage temperature ? 55 +150 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 89.3 k/w r th(c-a) thermal resistance from case to ambient in free air 60.6 k/w table 5. characteristics v ddd = v dda = 3.3 v; agnd and dgnd connected together; i o(fs) = 20 ma and t amb = ? 40 ? c to +85 ? c; typical values measured at t amb =25 ? c. symbol parameter conditions min typ max unit supplies v ddd digital supply voltage 3.0 3.3 3.65 v v dda analog supply voltage 3.0 3.3 3.65 v i ddd digital supply current f s = 65 msps, f o = 1 mhz, v dd = 3.0 v to 3.6 v -67 ma i dda analog supply current f s = 65 msps, f o = 1 mhz, v dd = 3.0 v to 3.6 v -5065 ma p tot total power dissipation f s = 65 msps, f o = 1 mhz, v dd = 3.0 v to 3.6 v - 185 260 mw p pd power dissipation in power-down mode - 16.5 - mw
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps digital inputs v il low-level input voltage dgnd - 0.9 v v ih high-level input voltage 1.3 - v ddd v i il low-level input current v il =0.9v - 5 - ? a i ih high-level input current v ih =1.3v - 5 - ? a c i input capacitance [1] -5- pf analog outputs (ioutap, ioutan, ioutbp and ioutbn) i o(fs) full-scale output current differential outputs 2 - 20 ma v o output voltage compliance range [1] ? 1-+1.25v r o output resistance [1] - 150 - k ? c o output capacitance [1] -3- pf reference voltage input/output (refio) v o(ref) reference output voltage 1.21 1.26 1.31 v i o(ref) reference output current [1] - 100 - na v i input voltage compliance range 1.0 - 1.26 v r i input resistance - 1 - m ? input timing, see figure 18 f s sampling frequency - - 125 msps t w(wrt) wrt pulse width pins wrta, wrtb 2 - - ns t w(clk) clk pulse width pins clka, clkb 2 - - ns t h(i) input hold time 1 - - ns t su(i) input set-up time 1.8 - - ns output timing (ioutap, ioutan, ioutbp and ioutbn) t d delay time - 1 - ns t t transition time rising or falling transition (10 % to 90 % or 90 % to 10 %) [1] -0.6- ns t s settling time ? 1lsb [1] -40- ns static linearity inl integral non-linearity 25 ? c ? 0.4 ? 0.55 ? 0.70 lsb ? 40 ? c to +85 ? c ? 0.3 - ? 0.75 lsb dnl differential non-linearity ? 40 ? c to +85 ? c ? 0.15 ? 0.2 ? 0.3 lsb static accuracy (relative to full-scale) with gainctrl = 0 e offset offset error ? 0.02 - +0.02 % e g gain error with external reference ? 1.9 ? 1.5 +2.5 % with internal reference ? 2.9 ? 2.1 +2.9 % ? g gain mismatch between dac a and dac b ? 0.5 ? 0.05 +0.5 % table 5. characteristics ?continued v ddd = v dda = 3.3 v; agnd and dgnd connected together; i o(fs) = 20 ma and t amb = ? 40 ? c to +85 ? c; typical values measured at t amb =25 ? c. symbol parameter conditions min typ max unit
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps [1] guaranteed by design. dynamic performance sfdr spurious free dynamic range b = nyquist f s = 52 msps; f o =1mhz 0 dbfs - 81 - dbc ? 6 dbfs - 80 - dbc ? 12 dbfs - 74 - dbc f s = 52 msps; 0 dbfs f o =5.24mhz - 79 - dbc f s = 78 msps; 0 dbfs f o =10.4mhz - 78 - dbc f o =15.7mhz - 71 - dbc f s = 100 msps; 0 dbfs f o =5.04mhz - 77 - dbc f o = 20.2 mhz 60 69 - dbc f s = 125 msps; 0 dbfs f o =20.1mhz - 68 - dbc within a window f s = 52 msps; f o = 1 mhz; 2mhzspan -89- dbc f s = 52 msps; f o = 5.24 mhz; 10 mhz span -87- dbc f s = 78 msps; f o = 5.26 mhz; 2mhz span -90- dbc f s = 125 msps; f o =5.04mhz; 10 mhz span 79 90 - dbc thd total harmonic distortion f s = 52 msps; f o = 1 mhz - ? 78 - dbc f s = 78 msps; f o =5.26mhz - ? 76 - dbc f s = 100 msps; f o =5.04mhz - ? 74 - dbc f s = 125 msps; f o =20.1mhz - ? 64 ? 60 dbc mtpr multitone power ratio f s = 65 msps; 2mhz DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps (1) f o =5mhz (2) f o =10mhz (3) f o =15mhz (4) f o =20mhz fig 3. sfdr as a function of the ambient temperature at 125 msps t ( c) ? 60 100 60 20 0 ? 20 001aai997 72 68 76 80 64 (1) (2) (3) (4) sfdr (dbc)
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps a. f s = 52 msps; f c =5.24mhz; ? =0dbfs b. f s =100msps; f c = 20 mhz; ? =0dbfs fig 4. 1-tone sfdr f (mhz) 0 30 20 10 001aai985 ? 60 ? 40 ? 80 ? 20 0 (dbm) ? 100 f (mhz) 0 50 40 20 30 10 001aai987 ? 60 ? 40 ? 80 ? 20 0 (dbm) ? 100
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps f s = 78 msps; f c = 9.44 mhz, f c = 10.44 mhz; ? =0dbfs fig 5. 2-tone sfdr f s = 52 msps; f c = 6.25 mhz, f c = 6.75 mhz, f c =7.25 mhz, f c = 7.75 mhz; ? =0dbfs fig 6. 4-tone sfdr f (mhz) 0 40 30 20 10 001aai988 ? 60 ? 40 ? 80 ? 20 0 (dbm) ? 100 f (mhz) 0 30 20 10 001aai989 ? 60 ? 40 ? 80 ? 20 0 (dbm) ? 100
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps f s = 78 msps; from f c = 9.5 mhz, 110 khz spacing; ? =0dbfs fig 7. 8-tone sfdr fig 8. inl as a function of the input code f (mhz) 0 40 30 20 10 001aai990 ? 60 ? 40 ? 80 ? 20 0 (dbm) ? 100 001aaj002 0 ? 0.4 0.4 0.8 inl (db) ? 0.8 input code 0 3720 2976 4464 2232 744 1488
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps fig 9. dnl as a function of the input code (1) f o =0dbfs (2) f o = ? 6dbfs (3) f o = ? 12 dbfs fig 10. sfdr full-scale at 78 msps as a function of the output frequency 001aaj001 0 ? 0.1 0.1 0.2 dnl (db) ? 0.2 input code 0 3780 3024 4536 2268 756 1512 f o (mhz) 0 20 15 10 5 001aaj040 85 sfdr (dbc) 60 65 70 75 80 (1) (2) (3)
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps (1) f o =0dbfs (2) f o = ? 6dbfs (3) f o = ? 12 dbfs fig 11. sfdr full-scale at 125 msps as a function of the output frequency (1) f s = 125 msps (2) f s = 100 msps (3) f s =78msps (4) f s =52msps fig 12. digital supply current as a function of f o /f s f o (mhz) 0 25 15 20 10 5 001aaj044 85 sfdr (dbc) 60 65 70 75 80 (1) (2) (3) f o /f s 0 0.5 0.3 0.2 0.1 001aai938 8 4 12 16 i ddd (ma) 0 0.4 (1) (2) (3) (4)
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10. application information 10.1 general description the DAC1201D125 is a dual 12-bit dac operating up to 125 msps. each dac consists of a segmented architecture, comprising a 7-bit thermometer sub-dac and a 5-bit binary weighted sub-dac. two modes are available for the digital input depending on the status of pin mode. in dual-port mode, each dac uses its own data input line at the same frequency as the update rate. in interleaved mode, both dacs use the same data input line at twice the update rate. each dac generates on pins ioutap/iout an and ioutbp/ioutbn two complementary current outputs. this provides a full-scale output current (i o(fs) ), up to 20 ma. a single common or two independent full-scale current c ontrols can be selected for both channels using pin gainctrl. an internal reference vo ltage is available for the reference current which is externally adju stable using pin refio. the DAC1201D125 operates at 3.3 v and has separate digital and analog power supplies. pin pwd is used to power-down the device. the digital input is 1.8 v compliant, 3.3 v compliant and 5 v tolerant. 10.2 input data the DAC1201D125 input follows a straight binary coding where da11 and db11 are the most significant bits (msb) and da0 and db0 are the least significant bits (lsb). the setting applied to pin mode defines whether the DAC1201D125 operates in dual-port mode or in interleaved mode (see table 6). fig 13. analog supply current as a function of the output current 001aaj032 l o (ma) 0 20 15 10 5 20 40 60 i dda (ma) 0
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.2.1 dual-port mode the data and clock circuit for dual-port mode operation is shown in figure 14. each dac has its own independent data and cl ock inputs. the data enters the input latch on the rising edge of the wrta/wrtb signal and is transferred to the dac latch. the output is updated on the rising edge of the clka/clkb signal. table 6. mode selection mode function da11 to da0 db11 to db0 pin 17 pin 18 pin 19 pin 20 low interleaved mode active off iqwrt iqclk iqreset iqsel high dual-port mode active active wrta clka clkb wrtb fig 14. dual-port mode operation fig 15. dual-port mode timing 12 12 001aai977 da11 to da0 wrta wrtb clka clkb input a latch dac a latch 12 12 db11 to db0 input b latch dac b latch 001aaj115 da11 to da0/ db11 to db0 n n+1 n ? 2n ? 1 n n+1 n+2 n+2 n+3 wrta/ wrtb clka/ clkb ioutap, ioutan/ ioutbp, ioutbn
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.2.2 interleaved mode the data and clock circuit for interleaved mode operation is illu strated in figure 16. in interleaved mode, both dacs use the same data and clock inputs at twice the update rate. data enters the latch on the rising edge of iqwrt. the data is sent to either latch a or latch b, depending on the value of iqsel. the iqsel transition must occur when iqwrt and iqclk are low. the iqclk is divided by 2 internally and the da ta is transferred to the dac latch. it is updated on its rising edge. when iqreset is high, iqclk is disabled, see figure 17. fig 16. interleaved mode fig 17. interleaved mode timing 001aai978 2 12 12 da11 to da0 iqwrt iqsel iqclk iqreset input a latch dac a latch 12 12 input b latch dac b latch 001aaj116 da11 to da0/ db11 to db0 n n+1 xx xx n+1 n n+3 n+5 n+2 n+4 n+2 iqreset ioutap, ioutan ioutbp, ioutbn n+3 n+4 n+5 n+6 n+7 iqsel iqwrt iqclk
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.3 timing the DAC1201D125 can operate at an update rate up to 125 msps. this generates an input data rate of 125 mhz in dual-port mode and 250 mhz in interleaved mode. the timing of the DAC1201D125 is shown in figure 18. the typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. ? a configuration resulting in the same timing for the signals wrta/wrtb and clka/clkb, can be achieved either by syn chronizing them or by connecting them together. ? the rising edge of the clka/clkb signal can also be placed in a range from half a period in front of the rising edge of the wrta/wrtb signal to half a period minus 1 ns after the rising edge of the wrta/wrtb signal. a typical set-up time of 0 ns and a hold time of 0.6 ns enables the DAC1201D125 to be easily integrated in to any application. 10.4 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: (1) the output current depends on the digital input data: fig 18. timing of the DAC1201D125 001aaj117 t su(i) t w(wrt) da11 to da0/ db11 to db0 wrta/ wrtb clka/ clkb ioutap, ioutan/ ioutbp, ioutbn t d(clk) t w(clk) 10 % 90 % t d t t t s t h(i) i ofs ?? i ioutp i ioutn + = i ioutp i ofs ?? data 4096 --------------- - ?? ?? ? = i ioutn i ofs ?? 4095 data ? ?? 4096 -------------------------------------- ?? ?? ? =
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps table 7 shows the output current as a function of the input data, when i o(fs) = 20 ma. 10.5 full-scale current adjustment the DAC1201D125 integrates one 1.25 v reference and two current sources to adjust the full-scale current in both dacs. the internal reference configuration is shown in figure 19. the bias current is generated by the output of the internal regulator connected to the inverting input of the internal operatio nal amplifiers. the external resistors r a and r b are connected to pins avires and bvires, respec tively. this configur ation is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. the relationship between full-scale output current (i o(fs) ) at the output of channel a or channel b and the resistor is: (2) the output current of the two dacs is typi cally fixed at 20 ma when both resistors r a and r b are set to 1.5 k ? . the operational range of DAC1201D125 is from 2 ma to 20 ma. it is recommended to decouple pin refio using a 100 nf capacitor. table 7. dac transfer function data da11/db11 to da0/db0 ioutap/ioutbp ioutan/ioutbn 0 0000 0000 0000 0 ma 20 ma ... ... ... ... 2047 1000 0000 0000 10 ma 10 ma ... ... ... ... 4095 1111 1111 1111 20 ma 0 ma fig 19. internal reference configuration 001aai822 1.25 v reference current source agnd agnd refio avires bvires r a current source agnd r b 100 nf i ofs ?? 24v refio r a ------------------------ =
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 19 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps an external reference can also be used for applications requiring higher accuracy or precise current adjustment. due to the high input impedance of pin refio, applying an external source disables the band gap. 10.6 gain control table 8 shows how to select the different gain control modes. in independent gain mode, both full-scale currents can be adjusted independently using resistors r a on pin avires and r b on pin bvires. in common gain mode, the full-scale cu rrent is adjusted with resistor r a on pin avires and divided by two in both dacs. 10.7 analog outputs see figure 20 for the analog output circuit of one dac. this circuit consists of a parallel combination of pmos current sources and associated switches for each segment. cascode source configuration enables the output impedance of the source to be increased, thus improving the dynamic performance by reducing distortion. the DAC1201D125 can be used with either: ? a differential output, coupled to a transformer (or operational amplifier) to reduce even-order harmonics and noise ? a single-ended output for applications requiring unipolar voltage a typical configuration is to use a 1 v p-p level on each output ioutap/ioutbp and ioutan/ioutbn. several combinat ions can be used but they must respect the voltage compliance range. table 8. gain control gainctrl mode dac a full-scale control dac b full-scale control low independent gain control avires bvires high common gain control avires avires fig 20. equivalent analog output circuit 001aai821 r l r l agnd agnd ioutap/ioutbp ioutan/ioutbn
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 20 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.7.1 differential output using transformer the use of a differential-coupled transforme r output (see figure 21) provides optimum distortion performance, and it helps to match the impedance and provides electrical isolation. the center tap is grounded to allow the dc curr ent flow to/from both outputs. if the center tap is open, the differential resistor must be replaced by two resistors connected to ground. 10.7.2 single-ended output using a single load resistor on one current outp ut will provide a unip olar outpu t range, typically from 0 v to 0.5 v with a 20 ma full-scale current at a 50 ? load. the resistor on the other current output is 25 ? . 10.8 power-down function the DAC1201D125 has a power-down function to reduce the power c onsumption when it is not active. fig 21. differential output with transformer 001aai935 ioutan/ ioutbn r diff r load ioutap/ ioutbp t1-1t 1:1 fig 22. single-ended output 001aai936 ioutan/ ioutbn 50 20 ma z = 50 50 0 v to 0.5 v ioutap/ ioutbp 25 low active 185 mw high not active 16.5 mw
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 21 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.9 alternative devices the following alternative devices are also available. table 10. alternative devices pin compatible type number description sampling frequency dac1001d125 dual 10-bit dac up to 125 msps dac1401d125 dual 14-bit dac up to 125 msps
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 22 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 10.10 application diagram dual-port mode (mode = high) dac active (pwd = low) independent channel gain (gainctrl = low) fig 23. application diagram DAC1201D125 001aaj125 1 n.c. da9 36 100 1.5 k 1.5 k 100 nf r l 100 r l 2 n.c. da10 35 3 db0 da11 34 4 db1 da8 33 5 db2 da7 32 6 db3 da6 31 7 db4 da5 30 8 db5 da4 29 9 db6 da3 28 10 db7 da2 27 11 db8 da1 26 12 db9 da0 25 13 mode n.c. 48 14 v dda n.c. 47 15 ioutap dgnd 46 16 ioutan v ddd 45 17 avires wrta/iqwrt 44 18 refio clka/iqclk 43 19 gainctrl clkb/iqreset 42 20 bvires wrtb/iqsel 41 21 ioutbn dgnd dgnd 3.3 v dgnd 3.3 v 40 22 ioutbp v ddd 39 23 agnd agnd 3.3 v agnd agnd agnd agnd agnd db11 38 24 pwd db10 37 100 nf 100 nf
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 23 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 11. package outline fig 24. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 24 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 12. abbreviations table 11. abbreviations acronym description dnl differential non-linearity dbfs decibel full-scale if intermediate frequency inl integral non-linearity lsb least significant bit msb most significant bit pmos positive-channel metal-oxide semiconductor sfdr spurious-free dynamic range
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 25 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 13. revision history 14. contact information for more information or sales office addresses, please visit: http://www.idt.com table 12. revision history document id release date data sheet status change notice supersedes DAC1201D125 v.3 20120702 product data sheet - DAC1201D125 v.2 DAC1201D125 v.2 20120127 product data sheet - DAC1201D125 v.1 modifications: ? table 4 ?thermal characteristics? has been updated. ? section 10.6 ?gain control? has been updated. DAC1201D125 v.1 20081127 product data sheet - -
DAC1201D125 3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 26 of 26 integrated device technology DAC1201D125 dual 12-bit dac, up to 125 msps 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 application information. . . . . . . . . . . . . . . . . . 14 10.1 general description . . . . . . . . . . . . . . . . . . . . 14 10.2 input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.2.1 dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 15 10.2.2 interleaved mode . . . . . . . . . . . . . . . . . . . . . . 16 10.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.4 dac transfer function. . . . . . . . . . . . . . . . . . . 17 10.5 full-scale current adjustmen t. . . . . . . . . . . . . 18 10.6 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7 analog outputs . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7.1 differential output using transformer . . . . . . . 20 10.7.2 single-ended output. . . . . . . . . . . . . . . . . . . . 20 10.8 power-down function . . . . . . . . . . . . . . . . . . . 20 10.9 alternative devices. . . . . . . . . . . . . . . . . . . . . 21 10.10 application diagram . . . . . . . . . . . . . . . . . . . . 22 11 package outline. . . . . . . . . . . . . . . . . . . . . . . . 23 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 24 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 25 14 contact information . . . . . . . . . . . . . . . . . . . . 25 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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